Henderson Nevada, September 11th , 2000 -- Aldec, Inc., a leading supplier of HDL design entry and verification software for programmable logic devices, announced today the industry's first mixed VHDL, Verilog and EDIF simulation and synthesis design environment, Active-HDLTM Express. The product is a combination of Aldec's Active-HDL design entry and mixed HDL simulation kernel together with SynopsysŪ [Nasdaq: SNPS] FPGA ExpressT synthesis software. Active-HDLTM Express is aimed at System-on-Chip (SoC) and high-density FPGA designs using multiple IP cores and a mixture of HDL design modules.

Quality - A New Paradigm for FPGA Designs

With growing FPGA device sizes and increased demands on time-to-market, designers must consider IP cores, design reuse, system level integration and EDA tool quality for successful designs. Since SoC designs require several distinctive processes such as design entry, synthesis and place and route, it is important to verify designs at each of these stages and capture errors before they propagate to other design phases. Active-HDL Express is the first EDA environment to support the simulation of post-synthesis EDIF netlists. This ability is critical because if not checked, design errors caused by inappropriate coding style, for example, could be passed to other software tools causing further complications and time sinks as the design process continues.

"Since Active-HDL Express uses EDIF netlist in its design flow, the same information is being processed by the simulator and implementation software, assuring quality designs"," states Gregor Siwinski, Director of Research and Development at Aldec. "

Mixed VHDL, Verilog and EDIF Capabilities

As FPGA and SoC design sizes continue to grow, the traditional approach to designing million-gate FPGAs and SoCs with separate best-in-class tools is no longer practical. Instead, designers require a totally integrated design environment that can deliver the necessary design quality and productivity. Replacing several tools with one integrated and reliable design environment cuts the learning curve and aids in meeting ambitious design schedules.

Active-HDL Express is the first EDA product supporting mixed VHDL, Verilog and EDIF designs, allowing users to enter, synthesize and simulate mixed language designs. Whether designing in VHDL or Verilog, the product is ideal for design teams with different language and IP core preferences. The freedom to reuse old design sections and choose a preferred HDL language for new design blocks speeds the design process.

" Designers of large FPGAs may have design files from different sources, in different formats. This can include: IP cores, reused designs, new logic, etc. We have bundled Synopsys FPGA Express, the only synthesis technology that supports design files from VHDL, Verilog and EDIF, with Active-HDL, which contains the only mixed kernel simulator that support VHDL, Verilog and EDIF. This means customers can simulate their high density FPGA designs at the behavioral, gate level (based on EDIF) and timing level using the same testbench, minimizing testbench development efforts." Quoted Michael O'Brien, Product Marketing Manager for Aldec.

Advantages of being able to Simulate EDIF

Active-HDL Express automatically sets the paths for all EDIF netlist files before they are passed to the FPGA place and route tool, allowing designers to perform gate level simulation of the entire design prior to place and route.

• Time Savings- a customer can instantly reuse a proven schematic module without redesigning it in HDL and retesting
• Cost Reduction - most IP Core companies provide IP cores in the EDIF format at a significant discount. If the model has been proven useful, the company can then order its source code for the product maintenance.
• Increased Productivity - the designer can use either VHDL or Verilog testbenches on designs that contain a mixture of VHDL, Verilog and EDIF modules.
• Faster Time-to-Market - simulating EDIF netlist of a synthesized design assures proper silicon behavior because it is the same netlist that is being passed to the place and route tools, which means moving product to market quicker.

VHDL or Verilog Testbench

Active-HDL Express allows the use of either VHDL or Verilog testbenches with mixed designs. For example, Verilog testbenches can be used with VHDL and EDIF designs and VHDL testbenches can be used with Verilog and EDIF designs. The designer does not need to create a new testbench if the supplied IP core is provided with either a Verilog or VHDL testbench because the original testbenches can be reused in Active-HDL Express without any limitation. This minimizes the number of design files and lowers design effort

Increased Productivity

Since Active-HDL Express supports VHDL, Verilog, EDIF and all FPGA and CPLD devices, designers no longer need to learn multiple design entry, simulation and logic synthesis products in order to design different devices. The experience gained with one design can be directly carried to the next one. Also, since the files are checked and transferred between applications automatically, the design process is faster, simpler, and less prone to errors. The ability to efficiently use design files for IP cores speeds the overall design cycle time.

Integration

Active-HDL Express has the highest level of tool integration in the EDA industry. The design editors, waveform viewers, debuggers, synthesis software, simulators and other applications are completely and seamlessly integrated, making Active-HDL Express a highly intuitive product. All software elements are controlled from the graphical Design Flow Manager that allows the selection of simulation, synthesis and place and route settings and viewing reports and cross-probe error messages. The seamless Push-button integration with the Synopsys FPGA Express synthesis allows simple access to this tool either directly though the GUI or by Tcl scripting for batch mode operation. Ease of use and higher productivity due to tight integration of all design tools are the key benefits of using the Design Flow Manager.

Availability

Active-HDL Express is available today and sold exclusively by Aldec. The product is available as either a permanent or time based license and includes Synopsys FPGA Express, HDL Project Manager, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer / Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation. To provide users with highest software quality, it comes included with one year of maintenance. All time-based licenses are issued for a period of 12-months and a 50% credit can be applied toward the purchase of a permanent license if made within the first year. To receive your FREE evaluation copy of Active-HDL Express, contact Aldec at www.aldec.com.

Active-HDL and Active-CAD are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners